1. Field of the Invention
The present invention relates to a level conversion circuit using insulated gate field effect transistors (MOS transistors). In particular, the present invention relates to a level shift circuit having a latch function and used for display devices formed using, for example, liquid-crystal elements or organic electroluminescence (EL) elements. More specifically, the present invention relates to a circuit configuration for latching and level-shifting a pixel data signal applied to a display pixel.
2. Description of the Background Art
In a display device using liquid-crystal elements or organic EL (electroluminescence) elements as display pixel elements, a level conversion circuit is employed for enlarging a signal amplitude. For example, in order to accurately drive the display pixel elements in accordance with a display signal, for achieving gradational display, the amplitude of an image data signal is enlarged to generate the display signal and supply the display signal to the pixel element.
For such a display device, it is generally required to reduce power consumption for preventing heat generation, and to reduce the power consumption in an application such as mobile equipment having a battery as a power source. Prior art document 1 (Japanese Patent Laying-Open No. 2003-115758) discloses a configuration of a level conversion circuit aiming to reduce power consumption.
In the configuration disclosed in the prior art document 1, an input signal is held in a first capacitance element in accordance with a sampling pulse. After this sampling is completed, a MOS drive stage having level conversion function is driven in accordance with the voltage held in the first capacitance element. In accordance with an output signal of the MOS drive stage, a second capacitance element is charged to generate a level-converted signal. With the configuration disclosed in the prior art document 1, it is intended to perform level conversion on the input signal with a smaller number of elements, in addition to reduction in power consumption.
Prior art document 2 (Japanese Patent Laying-Open No. 2002-358055) also discloses a level conversion circuit with an intention to reduce power consumption. In the level conversion circuit disclosed in the prior art document 2, a current-mirror type input buffer circuit for comparing an input signal with a reference voltage is activated for an activation period of a vertical scan start instruction signal, and an output signal of the current-mirror type input buffer circuit is latched by a latch circuit having level conversion function when the vertical scan start instruction signal is inactivated. The current-mirror type input buffer circuit is operated for a minimum necessary period of time, thereafter the output signal thereof is latched by the latch circuit and level conversion is performed by this latch circuit so as to reduce power consumption.
Moreover, prior art document 3 (Japanese Patent Laying-Open No. 2001-320268) discloses a level conversion circuit with the purpose of achieving a high-speed operation in addition to reduction of power consumption. In a configuration disclosed in the prior art document 3, an amplitude-limited control signal is generated in accordance with an input clock signal, and an output drive stage is driven in accordance with the amplitude-limited control signal. In limiting the amplitude, threshold voltage drop of a MOS transistor (insulated gate field effect transistor) is utilized, the output drive stage is constituted of a CMOS inverter, and one of the drive transistors is set to a strongly-on state while the other is set to a weakly-on state. The degree of the on state of the output drive transistors is simply controlled to achieve high-speed operation. Further, a transition period of the potential level on an output node is shortened to reduce the period in which a through current flows and thereby to reduce power consumption.
In addition, the prior art document 4 (Japanese Patent Laying-Open No. 2002-251174) discloses a configuration with the purpose of reducing power consumption of a level conversion circuit for enlarging a signal amplitude in an image display device. In the configuration disclosed in the prior art document 4, an output transistor has a gate clamped by diode-connected a MOS transistor, and further supplied with an input signal via a capacitance element. The gate potential of this output drive transistor is varied through capacitive coupling by the capacitance element and the output drive transistor is driven to an on/off state at a high speed, so that the through current is reduced and power consumption is reduced.
In a display device such as liquid-crystal display device, a thin-film transistor (TFT) is used as a MOS transistor. In this case, in order to prevent deterioration in characteristics of display pixel elements, a low-temperature polysilicon TFT is employed. Such a low-temperature polysilicon TFT is merely subject to annealing or heat treatment at a low temperature. Thus, as compared with a MOS transistor using single-crystal silicon, the crystal quality of the low-temperature polysilicon TFT is inferior. Therefore, in such TFTs, threshold voltage varies to a greater degree for different transistors and the channel resistance (ON resistance) in a conductive state is large.
In the configuration disclosed in the prior art document 1, in a level-converting operation, the output drive transistor is driven, in accordance with the input signal of small amplitude that is held in the first capacitance element, to discharge the voltage held in the second capacitance element. Therefore, the current drivability of the output drive transistor is small, and a level-converted signal of a large amplitude that is held in the second capacitance element cannot be discharged at a high speed, resulting in a problem that a high-speed operation is not ensured.
In the configuration disclosed in the prior art document 2, the current-mirror type buffer circuit is used for identifying the voltage level of the input signal. The input signal is compared with the reference voltage to generate the internal signal according to the result of this comparison, and the internal signal is latched by the latch circuit. Accordingly, the input buffer circuit has a large number of transistor elements, resulting in a problem that the occupied area cannot be reduced. In addition, if the transistor elements have greatly-varied threshold voltages, offset in a comparison stage of the current-mirror type input buffer circuit cannot be compensated for, resulting in a problem that an accurate input signal cannot be generated.
In the configuration disclosed in the prior art document 3, the gate potential of the transistor of the output drive stage for performing level conversion is level-shifted by the diode-connected MOS transistor. The degree of the ON state of the output drive transistors is changed in accordance with the input signal. Accordingly, in the output drive stage, both of charging and discharging drive transistors are in an ON state, resulting in a problem that a through current flows all the time.
In the configuration disclosed in the prior art document 4, the gate potential of the level-converting output drive transistor is clamped by the diode-connected MOS transistor. Through the capacitive coupling of the input signal, the gate potential of the drive transistors is changed. Accordingly, it is required to provide capacitance elements respectively for the high-side drive transistor and the low-side transistor on the node receiving the input signal, resulting in a problem that the load of the input signal increases. Further, the prior art document 4 disclosed a further configuration for driving an internal output node through capacitive coupling of an input signal. Specifically, between the gate of a first drive transistor and the internal output node, a capacitance element receiving the input signal is connected. The internal output node is further coupled to the input signal via a second drive transistor in accordance with an inverted signal of the input signal. Thus, if a skew occurs between the complementary input signals, the signal on the internal output node is coupled via the second drive transistor to the input signal, resulting in a problem that the internal output node cannot sufficiently charged and thus an accurately level-converted signal cannot be generated.